Integrated circuits (IC's) are prone to damage and failure caused by an electro-static-discharge (ESD) pulse. ESD failures that occur in the factory contribute to lower yields. ESD failures may also occur in the field when an end-user touches a device.
Various ESD-protection structures have been placed near input, output, or bi-directional I/O pins of ICs. Many of these protection structures use passive components such as series resistors, diodes, and thick-oxide transistors. Other ESD structures use an active transistor to safely shunt ESD current.
As manufacturing ability improves and device sizes shrink, lower voltages are applied to transistors during normal operation. These smaller transistors are much more susceptible to over-voltage failure but can operate with a lower power-supply voltage, thus consuming less power and producing less heat.
Such smaller transistors are often placed in an internal “core” of an IC, while larger transistors with gate lengths that are above the minimum are placed around the core in the periphery. ESD-protection structures are placed in the periphery using these larger transistors.
Thinner gate oxides of the core transistors can be shorted, and substrate junctions melted, by relatively small capacitively-coupled currents applied to the tiny core devices. Static charges from a person or machinery can produce such damaging currents that are only partially blocked by the input-protection circuits in the periphery.
FIG. 1 shows a chip with several ESD-protection clamps. Core circuitry 21 contains core transistors 22, 24, which have a small channel length and can be damaged by currents at relatively low voltages. Core circuitry 21 receives a power supply voltage VDD, such as 1.8 volts, 1.2 volts, or some other value. There may be thousands of core transistors in core circuitry 21.
Protection from ESD pulses may be provided on each I/O pad, and by power clamp 26. Power clamp 26 is coupled between VDD and ground (VSS), and shunts current from an ESD pulse between the power rails.
Each I/O pad 10 may be outfitted with one or more ESD protection devices 12, 16 to protect against various possibilities. ESD protection device 16 turns on for a positive ESD pulse applied from ground to I/O pad 10, while ESD protection device 18 turns on for a positive ESD pulse applied from ground to I/O pad 11. Likewise, ESD protection device 12 turns on for a positive ESD pulse applied from I/O pad 10 to VDD while ESD protection device 14 turns on for a positive ESD pulse applied from I/O pad 11 to VDD. Power clamp 26 may also turn on in some situations.
More recently, planar MOSFET devices are being replaced by FinFET. FinFET uses a more three-dimensional transistor structure where the transistor gate is no longer within one single plane. FinFET uses a smaller area and tend to have smaller leakages than traditional planar transistors.
FIG. 2 shows a prior-art FinFET device. N+ regions 42, 44 are formed on substrate 20 and are surrounded by oxide 62. Substrate 20 can be a silicon substrate or an insulator for Silicon-On-Insulator (SOI) processes. N+ regions 42, 44 are very thin, having a slim, fin-like appearance. Between N+ region 42 and N+ region 44 is a connecting region of lightly-p-doped silicon that acts as the transistor channel. N+ region 42, the channel connecting region, and N+ region 44 can all be formed on the same fin of silicon.
Gate 52 is formed around the channel connecting region. Rather than being flat, gate 52 has an inverted U-shape that surrounds the channel connecting region between N+ regions 42, 44. Gate oxide 60 is formed on three sides of the fin-like channel connecting region rather than only on the top surface of the channel region.
FinFET transistors may have better current drive than equivalent flat transistors for the same die area due to this 3-D gate and channel structure. However, when a FinFET transistor is used for ESD protection, the high ESD currents can damage the FinFET transistor. In particular, extreme heating is sometimes seen in N+ region 42 near the junction to the channel region under gate 52. This extreme heating when a large ESD current passes through N+ region 42 can permanently damage gate oxide 60 and N+ region 42, causing the device to leak or malfunction.
Also, the thin or slim size of the fin used for N+ region 42 causes the current to be crowded into a narrow region, causing localized hot spots. Heat dissipation is hindered by the slim fin of N+ region 42 that is typically surrounded by an insulator including oxide 62 and a passivation insulator that covers everything, including N+ region 42, oxide 62, and gate 52. Oxides and other insulators are often poor heat conductors.
FIG. 3 is a cross-section of a prior-art device with an ESD structure. N-wells 30, 50 and P-well 40 are formed in lightly-doped p-type substrate 54. Core circuits are formed in P-well 40, such as an NMOS transistor formed by gate 160 over gate oxide 162 between N+ regions 46 that act as source or drain regions. P-well 40 is biased to ground (VSS) through P+ tap 48, thus providing a back or body bias to all n-channel transistors formed within P-well 40.
Similarly, a p-channel transistor is formed in N-well 50 between source/drain P+ regions 36 that is controlled by gate 150 over gate oxide 152. N+ tap 38 connects N-well 50 to power VDD. Thus the body bias to all transistors in N-well 50 is set to VDD.
There may be many instances of N-well 50 and P-well 40 and some of these may be biased to other voltages. Some instances of N-well 50 could be floating, but all instances of P-well 40 will be biased to ground since p-type substrate 54 is in contact with P-well 40, and current can flow between P-well 40 and p-type substrate 54 so that both are biased to the same voltage.
An ESD protection structure is formed in N-well 30. An I/O pad connects to P+ region 34 in N-well 30, forming a PN diode. ESD current from this diode is collected by N+ taps 32 in N-well 30 that are connected to VDD. The PN diode may be a pad-to-VDD protection diode in an ESD structure. This ESD structure may be surrounded by a guard ring of P+ tap 54 in p-type substrate 54 that surrounds N-well 30.
In a typical complementary metal-oxide-semiconductor (CMOS) device, all wells are biased through well taps. P-well 40 is tapped by P+ tap 48 to ground, p-type substrate 54 is tapped by P+ tap 53 to ground, N-well 50 is tapped to VDD by N+ tap 38, and N-well 30 is tapped to VDD by N+ tap 32. Also, even if P+ tap 48 to P-well 40 were removed, P-well 40 would be biased by p-type substrate 54 since they are of the same conduction type.
ESD protection devices typically are much larger than core circuitry to permit high ESD currents to flow without damaging the ESD device. However, these large sizes are undesirable in that they have large capacitances that degrade high-frequency signals during normal chip operation. It is desirable to design ESD protection circuits that have a low capacitance to enhance high speed operation.
What is desired is an ESD-protection circuit that has lower parasitic capacitance. An ESD input-protection circuit that carries a high current but still has a low capacitance is desired. An ESD circuit for a Fin Field-Effect Transistor (FinFET) process is desired.